The present invention relates generally to the field of computer memory management, and more specifically to techniques for improving the efficiency of transactional memory.
Many computer systems employ cache memory to speed data retrieval operations. Cache memory stores copies of data found in frequently used main memory locations. Accessing data from cache memory speeds processing because cache memory can typically be accessed faster than main memory. If requested data is found in cache memory, then it is accessed from cache memory. However, if requested data is not found in cache memory, then the data is first copied into cache memory and then accessed from the cache memory.
Multi-level cache is an architecture in which there are multiple cache memories. For example, a computing system may have three levels, i.e. an L1 cache, an L2 cache, and an L3 cache. Typically, in a multi-level cache configuration, L1 would be the smallest and, thus, the easiest to search. If requested data is not found in L1 cache, the system searches L2 cache, which may be larger than L1 cache and, thus, take longer to search. In a similar fashion, if the data is not found in L2 cache, L3 cache is searched. Main memory is only searched after a determination has been made that the requested data is not in any of L1, L2, or L3 cache. Of course, there are many different implementations of cache memory.
Since the access time of a cache is often critical to the performance of a code that is executing, and a cache is often busy with many operations, it is beneficial to decrease a cache's workload, if possible. One common technique used to decrease a cache's workload includes accumulating multiple stores that store into to a common cache line in a cache line buffer, and then storing the contents of the cache line buffer into a cache as a single operation. This decreases a cache's workload and improves its response time and, thus, potentially improves the performance of a code that is executing. Such a technique is commonly performed in a mechanism called a store cache.
Transactional memory is a type of memory that groups multiple store operations performed by a processor into a single transaction that is visible to other processors as a single operation. The effects (e.g., the data) of multiple store operations participating in the single transaction are not made visible to other processors until the transaction is complete. Transactional memory is often helpful in synchronizing work that is performed in parallel on multiple CPUs.